Generally, the growth of integrated circuit industry depends on the continuous advancement in photolithographic technologies in integrated circuit manufacture. Propelled by advancement of photolithographic technologies, integrated circuits have repeatedly achieving the targets of higher density and smaller size. Hence, critical dimension (CD), including both minimum line width and space, of integrated circuits also has become finer and finer, indicating that higher resolutions are required. However, photolithographic resolution is fundamentally restricted by the wavelength of light sources used. To overcome such restriction, numerous methods provided by prior arts are available.
Referring to U.S. Pat. No. 5,618,383 issued to John N. Randall disclosing a low-temperature process for forming narrow lateral dimensioned microelectronic structures, this art comprises the steps of depositing and patterning an uncured photoresist on a supporting layer, at a low temperature using an anisotropic manufacturing process, depositing a conformal layer on sidewalls and on surfaces of the uncured photoresist with the conformal layer having substantial etch selectivity with respect to the photoresist, low-temperature anisotropic etching to remove the conformal layer from the surfaces of the uncured photoresist without substantially etching the conformal layer from vertical sidewalls, selectively removing the uncured photoresist to leave the isolated conformal layer, spin-coating of photoresist onto the isolated conformal layer and etching back to stop at the conformal layer, selectively etching to remove the conformal layer for forming an opening having a width as that of the conformal layer, and depositing a conductor to the opening, removing excessive conductor and photoresist for producing a narrow lateral dimensioned structure. However, structures formed using this method are prone to drawbacks as having relatively insufficient adherence.
Referring to U.S. Pat. No. 5,328,810 issued to Tyler A. Lowrey disclosing a method for reducing, by a factor of 2N, the minimum masking pitch of a photolithographic process, this art utilizes a conventional exposure and developing method for producing pattern of minimum line width F formable by photolithographic process onto a hard buffer layer, with the steps of reducing the line width of the hard buffer layer from F to F/2 by direct or indirect manner, depositing a second hard buffer layer having a relatively higher selective etch ratio to that of the hard buffer layer and underlayers, anisotropically etching to remove the second hard buffer layer on the top surfaces of the first hard buffer layer to leave the second hard buffer layer on the sidewalls of the first hard buffer layer, adopting the left sidewall second hard buffer layer as etch mask to reduce the pitch to ½ of the original pitch of mask pattern for that a width of the sidewall second hard buffer layer being F/4 at this point. The foregoing steps are repeated, and the minimum masking pitch of a photolithographic process is reduced by a factor of 2N. To be more precise, this method reduces a pitch by repeated deposition of conformal layers and anisotropic etching of hard buffer layers. However, this art has a drawback as the hard buffer layer being not so easily deposited.
Therefore, it is desired an improved method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution.